The structure of chips and links comprising the IBM eServer z990 I/O subsystem

chips and links comprising the IBM eServer z990 I/O subsystem E. W. Chencinski M. J. Becht T. E. Bubb C. G. Burwick J. Haess M. M. Helms J. M. Hoke T. Schlipf J. M. Turner H. Ulland M. H. Walz C. H. Whitehead G. Zilles The performance of large servers is to a high degree determined by their I/O subsystems. In the z990 server, nearly all of the components in the I/O path have been considerably improved in performance, capability, and cost. A 2-GB/s enhanced self-timed interface (eSTI) was introduced which is capable of absorbing the ever-increasing data rates of modern high-speed adapters. The I/O bandwidth available from a single node (three memory bus adapter, or MBA, chips, each with four eSTI ports) now equals 48 GB/s. As a consequence, both the MBA chip and the STI multiplexer switch (STI switch) chip had to be completely redesigned. In addition to these two chips, this paper describes the eSTI design itself and the Sweep chip, which integrates the function of four bidirectional adapter chips, one switch chip, and a clock chip.